1. Field of the Invention
The present invention relates generally to a power transistor device and a manufacturing method thereof, more particularly, to a trench type power transistor device with a super junction and a manufacturing method thereof.
2. Description of the Prior Art
In power transistor devices, the ON resistance (RDS(on)) between the drain and the source is proportional to the power consumption of the device, so an effective way to reduce the power consumption of the power transistor device is to lower the RDS(on). In power transistor devices, the resistance provided by the epitaxial layer used for withstanding high voltage is the main contribution to the RDS(on). Although increasing the doping concentration of the conductive material in the epitaxial layer can reduce the resistance, the breakdown voltage of the epitaxial layer will also be lowered, thereby degrading the capacity of the power transistor device to withstand high voltages. For this reason, a power transistor device with a super junction which has high voltage withstanding ability and low ON resistance has been developed in the industry.
Please refer to FIGS. 1-6, which are schematic views illustrating a manufacturing method of a conventional power transistor device with a super junction. First, as shown in FIG. 1, an N-type epitaxial layer 12 is deposited on an N-type substrate 10, and then an etching process is performed with a first photomask to etch a plurality of trenches 14 on the N-type epitaxial layer 12. As shown in FIG. 2, a P-type epitaxial layer 16 is then deposited in each trench 14 so that the upper surface of the P-type epitaxial layer 16 is leveled with the upper surface of the N-type epitaxial layer 12. Then, as shown in FIG. 3, an insulating layer 18 is covered on the N-type epitaxial layer 12 and the P-type epitaxial layer 16. Afterwards, a plurality of gate electrodes 20 are formed on the insulating layer 18 through utilizing a second photomask, wherein the gate electrodes 20 are disposed above the N-type epitaxial layer 12. As shown in FIG. 4, the gate electrode 20 serves as a mask, and a P-type ion implantation process is performed on the P-type epitaxial layer 16 and the N-type epitaxial layer 12 to form a P-type doped base region 22 in the P-type epitaxial layer 16 and N-type epitaxial layer 12. A thermal drive-in process is then performed to extend the P-type doped base region 22 to be overlapped with gate electrodes 20. Afterwards, an N-type ion implantation process is performed by using a third photomask to form two N-type doped source regions 24 in each P-type doped base region 22 adjacent to the gate electrodes 20. Then, as shown in FIG. 5, a dielectric layer 26 and a BPSG (boro-phospho-silicate-glass) layer 28 is covered on the gate electrodes 20 and the insulating layer 18. A photolithographic process and an etching process are then performed on the dielectric layer 26, the BPSG layer 28 and the insulating layer 18 on each P-type doped base region 22 to form a contact hole 30 on each P-type doped base region 22 and expose the P-type doped base regions 22. Then, as shown in FIG. 6, a P-type ion implantation process is performed to form a P-type doped contact region 32 in each P-type doped base region 22. A thermal drive-in process is performed to drive the P-type doped contact region 32 to contact each N-type doped source region 24. Finally, a contact plug 34 is filled into each contact hole 30 and a source metal layer 36 is formed on the BPSG layers 28 and the contact plugs 34. A drain metal layer 38 is formed under the N-type substrate 10. The N-type epitaxial layer 12 and the P-type epitaxial layer 16 constitute a vertical P-N junction, i.e. the so-called super junction. According to the above description, the conventional manufacturing method of the power transistor device needs up to four photomasks to define the patterns of different devices.
Although there are still other methods, such as performing multiple epitaxial processes and ion implantation processes to form super junctions in the industry, the cost and complexity for manufacturing the power transistor device will be significantly increased when the number of the photomasks used in the process is increased. In view of this matter, the main objective of the industry in the current stage is to lower the number of necessary photomasks and the complexity for manufacturing the power transistor devices.